EV20075DH-00A 3a, 1.30v ? 3.6v ddr memory vtt termination regulator EV20075DH-00A rev. 1.0 www.monolithicpower.com 1 10/10/2011 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description the mp20075 integrates the ddr memory termination regulator with the output voltage (vtt) and a buffered vttref whose output is half of vref. the vtt-ldo is a 3a sink/source tracking termination regulator. it is specifically designed for low-cost/low-external component count systems, where space is a premium. the mp20075 maintains a fast transient response only requiring 20uf (2x10 f) of ceramic output capacitance. the mp20075 supports kelvin sensing functions. the mp20075 is available in the 8-pin msop with exposed pad , package and is specified from ? 40 o c to 85 o c. electrical specifications parameter symbol value units input bias voltage v drv 3.3 v input voltage v ddq 1.3 - 1.8 v reference input voltage v ref v ddq v output voltage v tt 1/2 v ddq v output current i tt 3 a features ? vddq voltage range: 1.3v to 3.6v ? up to 3a integrated sink/source linear regulator with accurate vddq/2 divider reference for ddr termination ? requires only 20 f ceramic output capacitance ? drive voltage 3.3v ? 1.3v input (vddq) helps reduce total power dissipation ? integrated divider tracks vref for vtt and vttref ? kelvin sensing (vttsen) ? 30mv accuracy for vtt and vttref ? built-in soft-start, uvlo and ocl ? thermal shutdown applications ? notebook ddr2/3 memory supply and termination voltage in acpi compliant ? active termination busses ?mps? and ?the future of analog ic technology?, are trademarks of monolithic power systems, inc. EV20075DH-00A evaluation board (l x w x h) 2.5? x 2.5? x 0.5? (6.5cm x 6.5cm x 1.2cm) board number mps ic number EV20075DH-00A mp20075dh load regulation v ref =v ddq =1.8v output voltage v tt (v) load current ( a ) 0.86 0.88 0.90 0.92 0.94 0.96 -4 -3 -2 -1 0 1 2 3 4 v drv =3 . 0 v v drv =3 . 3 v
EV20075DH-00A ? 3a, 1.3v~3.6v input, ddr memory termination regualtor EV20075DH-00A rev. 1.0 www.monolithicpower.com 2 10/10/2011 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. evaluation board schematic EV20075DH-00A bill of materials qty ref value description package manufacturer manufacturer p/n 3 c1, c2, c3 10 f ceramic cap., 16v, x7r 1206 murata grm31cr71c106kac7l 2 c4,c6 0.1 f ceramic cap., 16v, x7r 0603 murata grm188r71c104ka01d 3 c5,c8, c9 ns 0603 1 c7 4.7 f ceramic cap., 16v, x7r 0805 murata grm21br71c475ka73l 1 r1 ns 0603 1 r2 100k ? film res., 5% 0603 yageo rc0603jr-07100kl 1 r3 20 ? film res., 5% 0603 yageo 9c06031a20r0jlhft 1 u1 ldo msop8 mps mp20075dh
EV20075DH-00A ? 3a, 1.3v~3.6v input, ddr memory termination regualtor EV20075DH-00A rev. 1.0 www.monolithicpower.com 3 10/10/2011 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. printed circuit board layout figure 1?top silk layer figure 2?top layer figure 3?bottom layer
EV20075DH-00A ? 3a, 1.3v~3.6v input, ddr memory termination regualtor notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. EV20075DH-00A rev. 1.0 www.monolithicpower.com 4 10/10/2011 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. quick start guide the output voltage of this board is set by vref vo ltage. the en pin is connected to vdrv with a 100k ? resistor for automatic startup. you can connect en to gnd to disable the mp20075. 1. attach the positive and negative ends of the load to the vtt and gnd pins, respectively. 2. attach the input voltage (1.3v vddq 3.6v) and input ground to the vddq and gnd pins, respectively. (the vref and vddq is directly connected together by r3) 3. attach the vdrv voltage 3.3v and ground to the vdrv and gnd pins, respectively. 4. the vtt output voltage is 1/2 of vref/vddq.
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